FIG. 1A shows bi-directional bus driver/receiver circuit 101 having a driver circuit 103 and a receiver circuit 104 that can drive data for a long distance data bus, which data bus may be more than several millimeters. The bi-directional driver circuit 103 and receiver circuit 104 provides a bus driver/receiver, for an example 2-bit bus 105, including a Din having Din[0] and Din[1] inputs for driver circuit 103 and a Dout having Dout[0] and Dout[1] outputs for receiver circuit 104. DrvClk is coupled to latch 106-0 and tri-state buffer 108-0 to provide output timing for data input at Din[0] and output to Dbus [0], and is coupled to latch 106-1 and tri-state buffer 108-1 to provide output timing for data input at Din[1] and output to Dbus [1]. Dbus [0] and Dbus[1] are arranged as a long distance bi-directional bus 105. RcvClk controls timing to receive data from Dbus[0] of Dbus 105 and to output the received data to Dout[0] from latch 119-0 that is coupled to Dbus [0] by buffer 109-0, and to receive data from Dbus[1] of Dbus 105 and to output the received data to Dout[1] from latch 119-1 that is coupled to Dbus [1] by buffer 109-1. FIG. 1B shows the data relationship between data input to the driver and output to the bi-directional bus with respect to DrvClk rise edge, where * refers to [0] or [1]. FIG. 1C shows the data relationship between data input to the receiver from the bi-directional bus and output from the receiver with respect to RcvClk rise edge, where * refers to [0] or [1].
A current is consumed every time the data shifts from high to low or low to high on a long distance bi-directional bus such as bus 105. In a desirable data bus configuration, number of bus lines is small, for example, two for 2-bit bus 105. However, a coupling effect can occur between the data bus lines such as Dbus [0] and Dbus[1] of data bus 105, and delay and timing mismatch occurs when data on the bus lines are shifted simultaneously. This undesirable effect, from data shifting simultaneously on bus lines, decreases a data valid window and can result in malfunction in a high bandwidth application.
FIG. 2A is a block diagram of a 4-bit data bus that uses bi-directional bus driver/receiver circuits 201-1, 201-2, 201-3, and 201-4, where each of these bi-directional bus driver/receiver circuits can be structured like bi-directional bus driver/receiver circuit 101 of FIG. 1. Bi-directional bus driver/receiver circuits 201-1 and 201-3 are connected together at different edges of a long distance bi-directional bus 205 by bus Dbus[0] and Dbus[1] of bi-directional bus 205, and bi-directional bus driver/receiver circuits 201-2 and 201-4 are connected together at different edges of long distance bi-directional bus 205 by bus Dbus[2] and Dbus[3] of bi-directional bus 205. Each of bi-directional bus driver/receiver circuits 201-2 and 201-1 includes two data inputs Din[3:2] and Din[1:0], respectively, to receive data DWin [3:0] as DWin [3:2] and DWin [1:0], respectively, and output this data to Dbus[3] and Dbus[2] from bi-directional bus driver/receiver circuit 201-2 and to Dbus[1] and Dbus[0] from bi-directional bus driver/receiver circuit 201-1, respectively. Each of bi-directional bus driver/receiver circuits 201-2 and 201-1 include two data outputs Dout[3:2] and Dout[1:0], respectively, to output received data DRout [3:0] as DRout [3:2] and DRout [1:0], respectively, which data is received from Dbus[3] and Dbus[2] at bi-directional bus driver/receiver circuit 201-2 and from Dbus[1] and Dbus[0] from bi-directional bus driver/receiver circuit 201-1, respectively.
Each of bi-directional bus driver/receiver circuits 201-4 and 201-3 include two data inputs Din [3:2] and Din[1:0], respectively, to receive data DRin [3:0] as DRin [3:2] and DRin [1:0], respectively, and output this data to Dbus[3] and Dbus[2] from bi-directional bus driver/receiver circuit 201-4 and to Dbus[1] and Dbus[0] from bi-directional bus driver/receiver circuit 201-3, respectively. Each of bi-directional bus driver/receiver circuits 201-4 and 201-3 include two data outputs Dout[3:2] and Dout[1:0], respectively, to output received, data DWout [3:0] as DWout [3:2] and DWout [1:0], respectively, which data is received from Dbus[3] and Dbus[2] at bi-directional bus driver/receiver circuit 201-4 and from Dbus[1] and Dbus[0] from bi-directional bus driver/receiver circuit 201-3, respectively.
DWClk provides write timing to DrvClk of bi-directional bus driver/receiver circuits 201-2 and 201-1 and to RcvClk of bi-directional bus driver/receiver circuits 201-4 and 201-3. DRClk provides read timing to RcvClk of bi-directional bus driver/receiver circuits 201-2 and 201-1 and to DrvClk of bi-directional bus driver/receiver circuits 201-4 and 201-3.
FIG. 2B shows a wiring arrangement for long distance bi-directional bus 205. It is desirable that only 4 wiring lines for 4-bit data extend adjacently to one another as shown in FIG. 2B. However, a shield bus may be used between two data wirings due to a parasitic capacitor effect between the two data bus. On the other hand, the negative effect due to parasitic capacitance can be avoided if a shield bus is inserted as shown in FIG. 2C with a shield line on each side and running adjacent to each of Dbus[0], Dbus[1], Dbus[2], and Dbus[3] of Dbus 205. However, the current consumption is still the same as FIG. 1A.
FIGS. 3A-3B are a timing chart for random data received at a Din [1:0] of the arrangement of FIG. 2A. Only received data. Dwin [1:0] is represented, where the data Dwin [1:0] is random. In the timing shown, the number of data change of Dbus [1:0] is 22 times. Loops 311-1, 311-2, 311-3, 311-4, 311-5, 311-6 show times that represent a case in which both 2 hits of data, one bit on Dbus[1] and one hit on Dbus[0], change at the same time. In this example, there are six cases in total of simultaneous changing of values of the bits. In the six cases, the device may have malfunctions, that is, delay of data, timing mismatch, or similar unwanted effect.
In addition, the maximum number of data bus switching at the same time is the same as number of data bus. In the case of FIGS. 3A-3B, the maximum number becomes two. Considering a product using large number of data bus lines like high bandwidth memory (HEM), the maximum peak current associated with data bus switching at the same time may have a negative effect on a system or peripheral circuits. In a general view, HBM is memory technology that uses through-substrate vias (TSVs) to interconnect stacked memory die. The Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association, a standards for the microelectronics industry, has published a High Bandwidth Memory (HBM) DRAM standard. In a JEDEC publication, the HBM standard provides wide input/out and TSV technologies in stacked memory devices to support high bandwidth operation, for example, support up to 8 GB per device at speeds up to 256 GB/s.